Data processing and generation of a timing pulse when a liquid crystal display device is driven are carried out using a logic circuit such as an integrated circuit (IC). Many of such circuits operate with a relatively small voltage amplitude of, for example, 0 V to 3.3 V. However, a voltage and a large amplitude beyond a range used in an ordinary logic circuit may be required such as when a signal is supplied to a gate line or a source line in driving a liquid crystal panel. In such a case, a level conversion circuit can convert a HIGH level (H level) potential and a LOW level (L level) potential of a rectangular wave generated by the ordinary logic circuit or the like, and generate a rectangular wave having an amplified amplitude.
When a level conversion circuit is formed of a CMOS circuit, it is necessary to use both a p-channel MOS transistor and an n-channel MOS transistor, which increases the number of manufacturing steps.
Therefore, in order to reduce the number of the manufacturing steps to improve the yield and to reduce the costs, a level conversion circuit is sometimes formed of MOS transistors of a single conductivity type.
FIG. 3 is a circuit diagram of a level conversion circuit disclosed in Japanese Patent Application Laid-open No. 2005-012356 described below. The level conversion circuit has a basic structure as an inverter circuit in which a driver circuit 2 and a load circuit 4 are connected in series between a high potential power supply VHIGH and a low potential power supply VLOW, and is configured to generate, in response to an input signal to the driver circuit, an output signal obtained by inverting the voltage change at a node between the driver circuit 2 and the load circuit 4. A source of an nMOS transistor M01 forming the driver circuit 2 is connected to the power supply VLOW, while a drain of the nMOS transistor M01 is connected to an output node NOUT. The load circuit 4 is a bootstrap circuit including an nMOS transistor M02 connected between the output node NOUT and the power supply VHIGH, an nMOS transistor M03 diode-connected between a gate of the nMOS transistor M02 and the power supply VHIGH, and a capacitor C connected between the gate of the nMOS transistor M02 and the output node NOUT.
For example, when a rectangular wave is input to an inverter having, as a driver transistor, an n-channel transistor disposed on the power supply VLOW side thereof, an ON resistance of the driver transistor is more reduced when the input signal which is the rectangular wave is at the H level than when the input signal is at the L level, to thereby drop a voltage at the output node. In this case, when the load circuit is the bootstrap circuit illustrated in FIG. 3, if the input signal is at the L level, the transistor M03 is in an OFF state in step with voltage rise at the output node NOUT. As a result, a gate potential of the transistor M02 rises to a potential higher than VHIGH-Vth (where Vth is a threshold voltage of the transistor M03) to promote voltage rise at the output node NOUT.
On the other hand, if the input signal is at the H level, the voltage at the output node NOUT drops. In this case, the transistor M03 is in an ON state, and the gate potential of the transistor M02 is basically VHIGH-Vth. In other words, while the ON resistance of the transistor M01 is reduced in accordance with the H level of the input signal, a gate-source voltage VGS of the transistor M02 rises in accordance with the voltage drop at the output node NOUT and an ON resistance of the transistor M02 is also reduced. Therefore, there is a problem in that, compared with a case in which the load circuit has a fixed resistance value, voltage drop at the output node NOUT is less steep and the output voltage is less liable to drop. There is another problem in that, because of the above-mentioned problem, it is difficult to increase the amplification factor of the output signal with respect to the input signal.
This application has been made to solve the problems described above, and an object of this application is to provide a level conversion circuit which can obtain a suitable amplification factor by using transistors of a single conductivity type, and to provide a liquid crystal display device using the same.